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1 united states patent no. 6,377,032 www.semtech.com sc1403 mobile multi-output pwm controller with lossless current sense power management revision 5, april 2004 description features applications typical application circuit the sc1403 is a multiple-output power supply controller designed to power battery operated systems. the sc1403 provides synchronous buck converter control for two (3.3v and 5v) power supplies. an efficiency of 95% can be achieved for the two supplies. the sc1403 uses semtech?s proprietary virtual current sense ? tech- nology along with external error amplifier compensation to achieve enhanced stability and dc accuracy over a wide range of output filter components while maintain- ing fixed frequency operation. lossless current sensing can be used to eliminate current sense resistors and reduce cost. the sc1403 also provides a 5v linear regu- lator for system housekeeping. the 5v linear regulator is derived from the battery; for improved efficiency, the output is switched to the 5v output when available. control functions include power-up sequencing, soft start, power-good signaling, and frequency synchronization. line and load regulation is to +/-1%. the internal oscillator can be set to 200khz, 300khz, or synchronized to an external clock. the mosfet drivers provide >1a peak drive current for fast mosfet switching. the sc1403 includes a psave# input to select pulse skip- ping mode for high efficiency at light load, or fixed fre- quency mode for low noise operation. ? 3.3v and 5v dual synchronous outputs, resistor programmable to 2.5v ? fixed frequency or psave operation for maximum efficiency over wide load range ? 5v / 50ma linear regulator ? virtual current sense ? for enhanced stability ? lossless current limiting ? out of phase switching reduces input capacitance ? external compensation supports wide range of output filter components ? programmable power-up sequence ? power good output ? output overvoltage and overcurrent protection with output undervoltage shutdown ? 6a typical shutdown current ? 6mw typical quiescent power ? notebook and subnotebook computers ? tablet pcs ? embedded applications
2 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com electrical characteristics absolute maximum ratings unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u s r e l l o r t n o c s p m s n i a m e g n a r e g a t l o v t u p n i 0 . 60 . 0 3v e l b a t s u j d a - e g n a r 5 b f , 3 b f e d o m , x b f = x l s c , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l t u p t u o 5 4 . 25 . 25 5 . 2v e d o m d e x i f - t u p t u o v 3 . 3, v 0 = 3 b f , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 3 3 2 . 33 . 37 3 . 3v e d o m d e x i f - t u p t u o v 5, v 0 = 5 b f , v 0 3 o t 0 . 6 = + v t i m i l t n e r r u c o t a 0 = d a o l v 5 9 . 40 . 51 . 5v e g n a r t s u j d a e g a t l o v t u p t u os p m s r e h t i ef e r5 . 5v d l o h s e r h t e d o m e l b a t s u j d a5 b f / 3 b f t a d e r u s a e m5 . 08 . 01 . 1v n o i t a l u g e r d a o l t i m i l t n e r r u c o t a 0 , s p m s r e h t i e4 . 0 -% n o i t a l u g e r e n i l v = # e v a s p ; 0 3 < + v < v 0 . 6 , s p m s r e h t i e l 5 0 . 0 exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. r e t e m a r a pn o i t p i r c s e dm u m i x a ms t i n u d n g o t 5 e s a h p , 3 e s a h p , + v , d d v s e g a t l o v e s a h p d n a y l p p u s0 3 + o t 3 . 0 -v d n g o t 5 e s a h p , 3 e s a h ps e g a t l o v e s a h p) c e s n 0 0 1 - t n e i s n a r t ( 0 . 2 -v d n g o t 5 h d , 3 h d , 5 t s b , 3 t s bs e g a t l o v t s o o b6 3 + o t 3 . 0 -v d n g o t d n g p d n u o r g l a n g i s o t d n u o r g r e w o p3 . 0 v d n g o t l vy l p p u s c i g o l6 + o t 3 . 0 -v ; 5 e s a h p o t 5 t s b ; 3 e s a h p o t 3 t s b y l p p u s e v i r d e t a g e d i s - h g i h6 + o t 3 . 0 -v 5 e s a h p o t 5 h d ; 3 e s a h p o t 3 h d s t u p t u o e v i r d e t a g e d i s - h g i h) 3 . 0 + x t s b + ( o t 3 . 0 -v d n g o t 5 l d , 3 l d d n g o t 3 h s c , 3 l s c , 5 h s c , 5 l s c s t u p t u o e v i r d e t a g e d i s - w o l s t u p n i e s n e s t n e r r u c d n a ) 3 . 0 + l v ( + o t 3 . 0 -v , # t e s e r , 5 n o , # e v a s p , q e s , c n y s , f e r d n g o t 5 p m o c , 3 p m o c , 5 b f , 3 b f , l v s t u p t u o / s t u p n i c i g o l) 3 . 0 + l v ( + o t 3 . 0 -v d n g o t # n d h s , 3 n o ) v 3 . 0 + + v ( + o t 3 . 0 -v d n g o t t r o h s f e r , l v s u o u n i t n o c t n e r r u c f e r 5 +a m t n e r r u c l v 0 5 +a m t j e g n a r e r u t a r e p m e t n o i t c n u j0 5 1 +c e c n a t s i s e r l a m r e h t e g a k c a pt n e i b m a o t n o i t c n u j6 7t t a w / c t s e g n a r e r u t a r e p m e t e g a r o t s0 0 2 + o t 5 6 -c t l e r u t a r e p m e t d a e l. x a m d n o c e s 0 1 , c 0 0 3 +c
3 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com electrical characteristics (cont.) unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u s d l o h s e r h t t i m i l - t n e r r u c ) 2 ( h s c x l s c - x ) t n e r r u c e v i t i s o p ( h s c x l s c - x ) t n e r r u c e v i t a g e n ( 0 45 5 0 5 - 0 7v m d l o h s e r h t g n i s s o r c o r e zh s c x l s c - x d e t s e t t o n , v 0 = # e v a s p5v m e m i t p m a r t r a t s - t f o s , t i m i l t n e r r u c l l u f % 5 9 o t e l b a n e m o r f f o t t c e p s e r h t i w c s o 2 1 5s k l c y c n e u q e r f r o t a l l i c s ol v = c n y s v 0 = c n y s 0 2 2 0 7 1 0 0 3 0 0 2 0 8 3 0 3 2 z h k r o t c a f y t u d m u m i x a ml v = c n y s v 0 = c n y s 2 9 4 9 4 9 6 9 % e s l u p h g i h t u p n i c n y sd e t s e t t o n0 0 3s n h t d i w e s l u p w o l t u p n i c n y sd e t s e t t o n0 0 3 e m i t l l a f / e s i r c n y sd e t s e t t o n0 0 2 e g n a r y c n e u q e r f t u p n i c n y s - 0 4 2 0 5 3 z h k e g a k a e l t u p n i 5 h s c , 3 h s c t n e r r u c v 0 . 5 = 5 h s c , v 3 . 3 = 3 h s c30 1a p m a r o r r e n i a g p o o l c d 5 p m o c / 3 p m o c o t e d o n k c a b d e e f l a n r e t n i m o r f8 1v / v t c u d o r p h t d i w d n a b n i a g 8z h m e c n a t s i s e r t u p t u o5 p m o c , 3 p m o c5 2s m h o k e c n e r e f e r d n a r o t a l u g e r l a n r e t n i e g a t l o v t u p t u o l v, v 0 3 < + v < v 6 ; + v = # n d h s i < a m 0 d a o l v 0 = 5 n o = 3 n o , a m 0 3 < 6 . 45 2 . 5v t u o k c o l e g a t l o v r e d n u l v d l o h s e r h t t l u a f v 7 . 0 = s i s e r e t s y h , e g d e g n i l l a f5 . 37 . 31 . 4 t u o k c o l r e v o h c t i w s l v e g d e g n i s i r - p u t r a t s t a r e v o h c t i w s5 . 4 e g a t l o v t u p t u o f e rd a o l l a n r e t x e o n5 4 . 25 . 25 5 . 2 n o i t a l u g e r d a o l f e ri < a 0 d a o l a 0 5 <5 . 2 1v m i < a m 0 d a o l a m 5 <0 5
4 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c k n i s f e rf e r n i e s i r v m 0 10 1a e g a t l o v t u o k c o l t l u a f f e re g d e g n i l l a f8 . 12 . 2v t n e r r u c y l p p u s g n i t a r e p o + v , n o s p m s h t o b , 5 t u o v o t r e v o d e h c t i w s l v a 0 = 5 d a o l i , a 0 = 3 d a o l i 0 10 5a t n e r r u c y l p p u s y b d n a t s + v, f f o s p m s , v 0 3 o t v 6 = + v # n d h s o t n i t n e r r u c s e d u l c n i 0 0 3 t n e r r u c y l p p u s n w o d t u h s + vv 0 = # n d h s , v 0 3 o t v 6 = + v1 -35 1 n o i t p m u s n o c r e w o p t n e c s e i u q , v 0 = 5 b f = 3 b f , d e l b a n e s p m s s p m s n o d a o l o n 6w m n o i t c e t e d t l u a f d l o h s e r h t p i r t e g a t l o v r e v o e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w71 15 1% t l u a f - e g a t l o v r e v o y a l e d n o i t a g a p o r p v p i r t e g a t l o v r e v o e v o b a % 2 n e v i r d t u p t u o h t 5 . 1s d l o h s e r h t e g a t l o v r e d n u t u p t u o e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w5 65 75 8% t u o k c o l e g a t l o v r e d n u t u p t u o e m i t f o t t c e p s e r h t i w , d e l b a n e s p m s h c a e m o r f c s o 0 0 0 54 4 1 60 0 0 7s k l c d l o h s e r h t n w o d t u h s l a m r e h tc 0 1 + = s i s e r e t s y h l a c i p y t0 5 1c # t e s e r d l o h s e r h t p i r t # t e s e r , e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w % 1 = s i s e r e t s y h l a c i p y t ; e g d e g n i l l a f 2 1 -9 -5 -% y a l e d n o i t a g a p o r p # t e s e r w o l e b % 2 n e v i r d t u p t u o , e g d e g n i l l a f d l o h s e r h t p i r t # t e s e r 5 . 1s e m i t y a l e d # t e s e rf o t t c e p s e r h t i w c s o 0 0 0 , 7 20 0 0 , 2 30 0 0 , 7 3 s k l c s t u p t u o d n a s t u p n i t n e r r u c e g a k a e l t u p n i k c a b d e e fv 6 . 2 = 5 b f , 3 b f1 -1a e g a t l o v w o l t u p n i c i g o l c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) f e r = q e s ( 6 . 0v e g a t l o v h g i h t u p n i c i g o l c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) f e r = q e s ( 4 . 2v electrical characteristics (cont.) unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
5 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com electrical characteristics (cont.) unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit note: (1) this device is esd sensitive. use of standard esd handling procedures required. (2) applicable for t a = 0 to +85 c r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c e g a k a e l t u p n i c n y s , 5 n o , # e v a s p f e r = q e s 1 -1a t n e r r u c e g a k a e l t u p n i 3 n ov 5 1 = 3 n o2 -2 t n e r r u c e g a k a e l t u p n i # n d h sv 5 1 = # n d h s1 -30 1a e g a t l o v w o l t u p t u o c i g o la m 4 = k n i s i , # t e s e r4 . 0v t n e r r u c h g i h t u p t u o c i g o lv 5 . 3 = # t e s e r1a m e c n a t s i s e r n w o d - l l u p 5 n o ) f e r = q e s ( , v 0 = 3 n o / n u r , 5 n o0 0 1s m h o t n e r r u c e c r u o s / k n i s r e v i r d e t a g v 5 . 2 o t d e c r o f , 5 h d , 5 l d , 3 h d , 3 l d1a e c n a t s i s e r - n o r e v i r d e t a g, 3 e s a h p o t 3 h d , 3 h d o t 3 t s b , 5 e s a h p o t 5 h d , 5 h d o t 5 t s b , d n g p o t 3 l d , 3 l d o t l v d n g p o t 5 l d , 5 l d o t l v 5 . 17 s m h o d l o h s e r h t p a l r e v o - n o n5 l d r o , 3 l d , 5 e s a h p , 3 e s a h p0 . 1v y a l e d h g u o r h t - t o o h s e g d e g n i s i r x l d o t e g d e g n i l l a f x h d e g d e g n i s i r z h d o t e g d e g n i l l a f x l d , x l d d n a x h d n o d l o h s e r h t v 1 ( ) . x h d / x l d n o e c n a t i c a p a c l a n r e t x e o n 0 1 5 3 7 1 5 7 5 2 5 1 1 c e s n
6 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com pin configuration ordering information e c i v e de g a k c a pt ( . p m e t a ) r t s t i 3 0 4 1 c s8 2 - p o s s tc 5 8 + - 0 4 - t r t s t i 3 0 4 1 c s8 2 - p o s s t n o i t p o e e r f - d a e l c 5 8 + - 0 4 - block diagram 1 2 3 4 5 6 7 8 on3 csh3 top view (28 pin tssop) 27 28 15 16 dh3 csl3 phase3 fb3 bst3 comp3 dl3 comp5 shdn# sync v+ on5 vl gnd 9 10 22 pgnd ref dl5 psave# 21 18 17 19 20 11 12 24 bst5 reset# phase5 fb5 23 25 26 13 14 dh5 csl5 seq csh5 (1) only available in tape and reel packaging. a reel contains 2500 devices. note:
7 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com pin descriptions # n i pe m a n n i pn o i t c n u f n i p 13 h s c. s p m s v 3 . 3 r o f t u p n i e s n e s t n e r r u c e d i s - h g i h r o , k r o w t e n c r r c d e h t f o e d i s h g i h e h t o t t c e n n o c . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t o t 23 l s c , n o i t a r e p o e d o m e l b a t s u j d a r o f . s p m s v 3 . 3 r o f t u p n i e s n e s t n e r r u c e d i s w o l v 3 . 3 e h t o t t c e n n o c . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t r o , k r o w t e n c r r c d e h t f o e d i s w o l e h t r e h t i e t a , t u p t u o t u p n i e s n e s k c a b d e e f e h t s a s e t a r e p o o s l a 3 l s c d n a , d e d n u o r g s i 3 b f , n o i t a r e p o t u p t u o - d e x i f r o f . s p m s v 3 . 3 e h t r o f 33 b f 3 b f , ) s r o t s i s e r k c a b d e e f l a n r e t x e g n i s u ( e d o m e l b a t s u j d a n i . s p m s v 3 . 3 e h t r o f t u p n i k c a b d e e f . t u p t u o v 3 . 3 d e x i f a t e s s r o t s i s e r l a n r e t n i , d e d n u o r g s i 3 b f n e h w . ) v 5 . 2 ( f e r o t s e t a l u g e r 43 p m o c. r e i f i l p m a r o r r e v 3 . 3 e h t f o t u p t u o n o i t a s n e p m o c 55 p m o ct u p t u o n o i t a s n e p m o c. r e i f i l p m a r o r r e v 0 . 5 e h t f o 6c n y s r o f d n g o t e i t ; n o i t a r e p o z h k 0 0 3 r o f l v o t e i t . t c e l e s y c n e u q e r f d n a n o i t a z i n o r h c n y s r o t a l l i c s o . z h k 0 5 3 d n a z h k 0 4 2 n e e w t e b e z i n o r h c n y s o t y l l a n r e t x e e v i r d . z h k 0 0 2 75 n o v 5 w o l l a o t 5 n o h t i w s e i r e s n i r o t s i s e r m h o k 0 1 - k 1 a t c e n n o c . t u p n i l o r t n o c f f o / n o v 5 . n w o d t u h s 8d n g. t n i o p e c n e r e f e r k c a b d e e f d n a d n u o r g g o l a n a e s i o n w o l 9f e r . m u m i n i m f 1 h t i w d n g o t s s a p y b . t u p t u o e g a t l o v e c n e r e f e r v 5 . 2 0 1# e v a s p . e s u l a m r o n r o f d n g o t t c e n n o c . h g i h n e h w e d o m e v a s p s e l b a s i d t a h t t u p n i l o r t n o c c i g o l 1 1# t e s e r k c o l c 0 0 0 , 2 3 d e x i f a r e t f a h g i h s e o g . l v o t d n g s g n i w s # t e s e r . t u p t u o t e s e r d e m i t w o l e v i t c a . p u r e w o p l u f s s e c c u s a g n i w o l l o f y a l e d e l c y c 2 15 b f 3 b f , ) s r o t s i s e r k c a b d e e f l a n r e t x e g n i s u ( e d o m e l b a t s u j d a n i . s p m s v 5 e h t r o f t u p n i k c a b d e e f . t u p t u o v 5 d e x i f a t e s s r o t s i s e r l a n r e t n i , d e d n u o r g s i 5 b f n e h w . ) v 5 . 2 ( f e r o t s e t a l u g e r 3 15 l s c v 5 e h t o t t c e n n o c , n o i t a r e p o e d o m e l b a t s u j d a r o f . s p m s v 5 r o f t u p n i e s n e s t n e r r u c e d i s w o l . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t r o , k r o w t e n c r r c d e h t f o e d i s w o l e h t r e h t i e t a , t u p t u o t u p n i e s n e s k c a b d e e f e h t s a s e t a r e p o o s l a 5 l s c d n a , d e d n u o r g s i 5 b f , n o i t a r e p o t u p t u o - d e x i f r o f . s p m s v 5 e h t r o f 4 15 h s c o t r o , k r o w t e n c r r c d e h t f o e d i s h g i h e h t o t t c e n n o c . s p m s v 5 r o f t u p n i e s n e s t n e r r u c e d i s - h g i h . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t 5 1q e s. # t e s e r r o f e c n e u q e s s p m s s t c e l e s t a h t t u p n i 6 15 h d. h c t i w s l e n n a h c - n e d i s h g i h , v 5 e h t r o f t u p t u o e v i r d e t a g 7 15 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s s p m s v 5 8 15 t s b. e v i r d e t a g e d i s h g i h v 5 r o f n o i t c e n n o c r o t i c a p a c t s o o b note: all logic level inputs and outputs are open collector ttl compatible.
8 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com pin descriptions (cont.) # n i pe m a n n i pn o i t c n u f n i p 9 15 l d . t e f s o m r e i f i t c e r s u o n o r h c n y s e d i s w o l v 5 e h t r o f t u p t u o e v i r d e t a g 0 2d n g p. d n u o r g r e w o p 1 2l v t u p t u o s p m s v 5 o t s t c e n n o c l v , y c n e i c i f f e d e v o r p m i r o f . t u p t u o r o t a l u g e r r a e n i l l a n r e t n i v 5 . d e l b a n e s i s p m s v 5 n e h w 2 2+ v. t u p n i e g a t l o v y r e t t a b 3 2# n d h s. w o l e v i t c a , t u p n i l o r t n o c n w o d t u h s 4 23 l d . t e f s o m r e i f i t c e r s u o n o r h c n y s e d i s w o l v 3 . 3 e h t r o f t u p t u o e v i r d e t a g 5 23 t s b. e v i r d e t a g e d i s h g i h v 3 . 3 r o f n o i t c e n n o c r o t i c a p a c t s o o b 6 23 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s v 3 . 3 7 23 h d. h c t i w s l e n n a h c - n e d i s h g i h , v 3 . 3 e h t r o f t u p t u o e v i r d e t a g 8 23 n o. t u p n i l o r t n o c f f o / n o v 3 . 3 note: all logic level inputs and outputs are open collector ttl compatible. block diagram
9 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com functional information detailed description the sc1403 is a versatile multiple-output power supply controller designed to power battery operated systems. the sc1403 provides synchronous rectified buck control in fixed frequency forced- continuous mode and hysteretic psave mode, for two switching power supplies over a wide load range. out of phase switching improves signal quality and reduces input rms current, therefore reducing size of input filter inductors and capacitors. lossless current sensing eliminates the need for discrete current sense resistors. the two switchers have on-chip preset output voltages of 5.0v and 3.3v. an external resistor divider can be used to set the switcher outputs from 2.5v to 5.5v. the control circuitry for each pwm controller includes digital softstart, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, overcurrent, overvoltage and undervoltage fault protection. one linear regulator and a precision reference voltage are also provided. the 5v/30ma linear regulator uses battery power to feed the gate drivers; for improved efficiency the 5v switcher output is used instead when available. semtech?s proprietary virtual current sense tm provides greater advantages in the aspect of stability and signal-to-noise ratio than the conventional current sense method. pwm control there are two separate pwm control blocks for each switcher. they are switched out-of-phase with each other. the interleaved topology reduces steady state input filter requirements by reducing current drawn from the filter capacitors. to avoid both switchers switching at the same instance, there is a built-in delay between the turn-on of the 3.3v switcher and 5v switcher, the amount of which depends on the input voltage (see out-of-phase switching). the pwm provides two modes of control over the entire load range. the sc1403 operates in forced continuous conduction mode as a fixed frequency peak current mode controller with falling edge modulation. current sense is done differently than in conventional peak current mode control. semtech?s proprietary virtual current sense tm emulates the necessary inductor current information for proper functioning of the ic. in order to accommodate a wide range of output filters, a comp pin is also available for compensating the error amplifier externally. a nominal gain of 18 is used in the error amplifier to further improve the system loop gain response and the output transient behavior. when the switcher is operating in continuous conduction mode, the high-side mosfet is turned on at the start of each switching cycle. it is turned off when the desired duty cycle is reached. active shoot-through protection delays the turn-on of the lower mosfet until the phase node drops below 1v. the low-side mosfet remains on until the beginning of the next switching cycle. again, active shoot-through protection ensures that the gate to the low-side mosfet has dropped low before the high-side mosfet turns on. under light load conditions when the psave# pin is low, the sc1403 operates as a hysteretic controller in the discontinuous conduction mode to reduce its switching frequency and switching bias current. the switching of the output mosfet does not depend on a given oscillator frequency, but on the hysteretic feedback voltage set around the reference. when entering psave# mode, if the minimum (valley) inductor current measured across the csh and csl pins is below the psave# threshold for four switching cycles, the virtual current sensing circuitry is shutdown and pwm switches from forced continuous to hysteretic mode. if the minimum (valley) inductor current is above the threshold for four switching cycles, pwm control changes from hysteretic to forced continuous mode. the sc1403 provides built-in hysteresis to inhibit chattering between the two modes of operation. gate drive / control the gate drivers on the sc1403 are designed to switch large mosfets up to 350khz. the high-side gate driver is required to drive the gates of high-side mosfet above the v+ input. the supply for the gate drivers is generated by charging a boostrap capacitor from the vl supply when the low-side driver is on. monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. in continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. under light load conditions when psave# pin is low, the inductor ripple current will approach the point where it reverses polarity. this is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. the low-side driver operation is also affected by various fault conditions as described in the fault protection section. internal bias supply the vl linear regulator provides a 5v output used to power the gate drivers, 2.5v reference and internal control section of the sc1403. the regulator is capable of supplying up to 30ma (in- cluding mosfet gate charge current). the vl pin should be bypassed to gnd with 4.7uf to supply the peak current requirements of the gate driver outputs. the regulator receives its input power from the v+ battery input. efficiency is improved by providing a boot-strapping mode for the vl bias. when the 5v smps output voltage reaches 5v, internal circuitry turns on a pmos pass device between csl5 and vl. the internal vl regulator is then disabled and vl bias is provided by the high efficiency 5v switcher. the ref output is accurate to +/- 2% over temperature. it is capable of delivering 5ma max and should be bypassed with 1uf minimum capacitor. loading the ref pin will reduce the ref voltage slightly as shown in the following table.
10 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com functional information (cont.) g n i d a o l e c n a t s i s e r ) m h o ( 1 1 5k 7 6 . 2k 9 . 9 4k 5 5 2g e m 1 f e r v n o i t a i v e d v m 3 . 8v m 1 . 3v m 5 . 0v m 3 . 0v m 0 current sense (csh, csl) output current of each supply is sensed as the voltage between the csh and csl pins. overcurrent is detected when the current sense voltage exceeds +55/-50 mv typical. a positive overcurrent turns off the high-side driver, a negative overcurrent turns off the low-side driver; each on a cycle-by-cycle basis. output current can be sensed by dcr (lossless) sensing, or optionally with a current- sense resistor; see applications information. oscillator when the sync pin is high the oscillator runs at 300khz; when sync is low the frequency is 200khz. the oscillator can be synchronized to the falling edge of a clock on the sync pin with a frequency between 240khz and 350khz. in general, 200khz operation provides highest efficiency, while 300khz is used to obtain smaller output ripple and/or smaller filter components. fault protection in addition to cycle-by-cycle current limit, the sc1403 provides overtemperature, output overvoltage, and undervoltage protection. overtemperature protection will shut the device down if die temperature exceeds 150 c, with 10 c hysteresis. if either smps output is more than 10% above its nominal value, both smps are latched off and the low side mosfets are latched on. to prevent the output from ringing below ground in a fault condition, a 1a schottky diode should be placed across each output. two different levels of undervoltage (uv) are detected. if the output falls 9% below its nominal value, the reset# output is pulled low. if the output falls 25% below its nominal value, both smps are latched off. both of the latched faults (ovp and uv) persist until shdn or on3 is toggled, or the v+ input is brought below 1v. shutdown and operating modes holding the shdn pin low disables the sc1403, reducing the v+ input current to less than 10ua. when shdn is high, the part enters standby mode where the vl regulator and vref are enabled. turning on either smps will put the sc1403 in run mode. n d h s3 n o5 n oe d o mn o i t p i r c s e d w o lxx - t u h s n w o d s a i b m u m i n i m t n e r r u c h g i hw o lw o ly b d n a t sl v d n a f e r v r o t a l u g e r e l b a n e h g i hh g i hh g i hn u r e d o m s p m s h t o b g n i n n u r output voltage selection if fbx is grounded, internal resistors determine 3.3v and/or 5v output voltages. in adjustable mode, the internal resistors are disabled and the output is determined by external resistors, based on 2.5v regulated at the fb pin. the output voltage is determined according the following formula. rdown should not exceed 10 kohms. rup rdown 3v or 5v fb3 or fb5 ? ? ? ? ? ? + ? = rdown rup vout 1 5 . 2 power up controls and soft start the user controls the sc1403 reset# through the seq, on3 and on5 pins, as shown in the startup sequence chart. at startup, reset# is held low for 32k switching cycles, and then reset# is determined by the output voltages and the seq pin. to prevent surge currents at startup, each smps has a counter and dac to incrementally raise the current limit (csh-csl voltage). the current limit follows discrete steps of typically 25%, 40%, 60%, 80%, and 100%, each step lasting 128 clock cycles. to charge up the output capacitors, inductor current at startup must exceed load current. when the output voltage reaches it?s nominal value the smps will reduce duty cycle, but the excess li 2 energy of the inductor must flow into the load and output capacitors. if the output capacitor is relatively small, the peak output voltage can approach the overvoltage trip point. to prevent nuisance ovp at startup, the inductance and capacitance must meet the following criteria: 59 . 1 2 2 _ _ ? oc max nom o min max il v c l il max_oc is the maximum inductor current set by the current-limit components, and v o_nom is the nominal output voltage.
11 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com startup sequence chart functional information (cont.) q e s3 n o5 n ot e s e rn o i t p i r c s e d f e rw o lw o l. s p m s v 3 . 3 s w o l l o f . f f o s s p m s h t o b . e d o m l o r t n o c t r a t s t n a d n e p e d n i f e rw o lh g i h. w o l. f f o s p m s v 3 . 3 , n o s p m s v 5 f e rh g i hw o l. s p m s v 3 . 3 s w o l l o f. f f o s p m s v 5 , n o s p m s v 3 . 3 f e rh g i hh g i h. s p m s v 3 . 3 s w o l l o f. n o s s p m s h t o b d n gw o lx . w o l. f f o s s p m s h t o b d n gh g i hw o l / h g i he r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r n i , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 5 . f f o s i v 3 , w o l = 5 n o f i . n o s i v 3 l vw o lx . w o l. f f o s s p m s h t o b l vh g i hw o l / h g i he r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r n i , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 3 . f f o s i v 5 , w o l = 5 n o f i . n o s i v 5 applications information reference circuit design the schematic for the reference circuit is shown on page 27. the reference circuit is configured as follows: switching regulator 1 vout1 = 3.3v @ 6a switching regulator 2 vout2 = 5.0v @ 6a linear regulator vout3 = 5.0v @ 50ma input voltage vin = 7 to 21v designing the output filter before calculating the filter inductance and capacitance, an acceptable inductor ripple current is determined. maximum allowable ripple depends on the transient requirements. ripple current is usually set at 10% to 20% of the maximum load. however, increasing the ripple current allows for a smaller inductor and will also quicken the output transient response. in this example, we set the ripple current to be 25% of maximum load. a a i o 5 . 1 6 % 25 = = ? the inductance is found from ripple current, frequency, input voltage, and output voltage. minimum required inductance is found at maximum vin, where ripple current is the greatest. uh io f vin vo vo min l 18 . 6 ) / 1 ( = ? ? = the next standard value is 6.8uh. for the reference design, the coiltronics dr127-6r8 is used. to specify the output capacitance, the allowable output ripple voltage must be determined. output ripple is often specified at 1% of the output voltage. for the 3.3v output, we selected a maximum ripple voltage of 33mvp-p. the maximum allowable esr would then be: ? = = ? ? = m a mv i v esr o o max 22 5 . 1 / 33 / panasonic sp polymer aluminum capacitors are a good choice. for this design, use one 180uf, 4v device, with esr of 15m ? . the output capacitor must support the inductor rms ripple current. to check the actual ripple versus the capacitor?s rms rating: a a i i o actual rms 43 . 0 12 5 . 1 12 _ = = ? = this is much less than the capacitor?s ripple rating of 3.3a. choosing current sense components since the sc1403 implements virtual current sense tm , current sensing is not required for the control loop. but it is required for cycle-by-cycle current limit and for startup. cycle-by-cycle current limit is reached when the voltage of csh-csl exceeds 55mv nomi- nal. depending on the system requirement, this current limit can vary, but it is typically 10% to 30% higher than the maximum load. this design uses the dc resistance of the inductor as a current sense element, which eliminates the cost and space required for a separate current sense resistor. below is a typical dcr applica- tion circuit. the inductor is shown along with it?s wiring resistance rl. in place of the current sense resistor are c, r2, and r1, which are connected across the inductor terminals.
12 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com applications information (cont.) c r1 r2 l rl csh csl vo vlx (phase node) (output) the equation for the current sense signal, csh - csl, is given by: 1) (eq r1 r2 sc r1 r2 r2 ) v (v v o lx csl) (csh ? ? + + ? ? = ? where (v lx - vo) is the voltage across the inductor terminals. the values for c, r2, and r1 can be found by comparing the above circuit with resistive sensing, which is shown below. rsns sl vlx rl vo (output) (phase node) csh csl with resistive sensing, the current sense signal csh-csl can be written in the complex s-domain as: 2) (eq sl rl rsns rsns v v v o lx csl csh + + ? ? = ? ) ( ) ( where (v lx - vo) is the voltage across the inductor terminals. note the similarity between eq 1 and eq 2. by choosing proper values for c, r1, and r2, the current-sense voltage (csh-csl) will track the inductor current. the following equations determine c, r1, and r2: 55mv c ilpk l r1 ? ? = () 55mv rl ilpk 55mv r1 r2 ? ? ? = the recommended value for c is 1.0uf. rl inductor resistance is specified at 11.6 mohm typical. 55mv is the current sense thresh- old. for the reference design, the values are set to c = 1uf and r1 = r2 = 1.3k. this sets the current limit to approximately 10a. two guidelines must be used when selecting c, r1, and r2: the values of r2 and r1 should not exceed approximately 1.5kohm. the bias current from the csh input flows through these resistors and creates an error term. the value for r1 should not be too small due to power consider- ations. during a switching cycle, the voltage across r1 is either (vin - vo) or (-vo). this creates a power loss in r1: the power loss can be determined by: () () mw 45 k 1 r1 vo - vin vo p 1 r = ? ? ? = ? = 3 . 3 . 3 21 3 . 3 choosing the main switching mosfet the irf7143 is used in the reference design. before choosing the main (high-side) mosfet, we need to check three parameters: volt- age, power, and current rating. the maximum drain to source voltage of the mosfet is mainly determined by the switcher topology. since this is a buck topology, v 21 v v max _ in max _ ds = = the irf7413 is a 30v device, which allows for 70% derating at 21v operation. the mosfet power dissipation has three components: conduction losses, switching losses, and gate drive losses. the conduction loss is determined using the rms mosfet current; the equation is shown below. the mosfet current is a trapezoid waveform with values equal to: 2 l load min i i i ? ? = 2 l load max i i i ? + = l fs d vo i l ? ? ? = ? ) 1 ( vin vo d = () 2 2 max max min min rms i i i i d i + ? + ? = as input voltage decreases, the duty cycle increases and the ripple current decrease, and overall the rms mosfet current will increase. the conduction losses are then given by the formula below, where rds(on) is 18m-ohm for the irf7413 at room temperature. note that rds(on) increases with temperature. 2 ) ( rms on ds conduction i r p ? = the mosfet switching loss is estimated according to: g out s in rss switching i i f v c p ? ? ? = 2 crss is the reverse transfer capacitance of the mosfet, which is 240pf for irf7413. ig is the gate driver current, which is 1a for sc1403. the mosfet gate drive loss is estimated from:
13 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com applications information applications information (cont.) . s 2 g gate f v c 2 1 p ? ? ? = cg is the effective gate capacitance, equal to the total gate charge divided by vgs from the vendor datasheet, and is 7.9nf for the irf7413. v in the above formula is the final gate-source voltage on the mosfet, 5v for the sc1403. the total mosfet losses is the sum of the three loss components. gate switching conduction diss _ total p p p p + + = the mosfet dissipation under conditions of 15v input, 6a load, and ambient temperature of 25c, can be determined as: dnom = 0.22 ? il = 1.26a imin = 5.37a imax = 6.63a irms = 4.88a rds(on) (100c) = 18 mohm pconduction = 429mw pswitching = 97mw pgate = 30mw ptotal_diss = 429 + 97 + 30 = 556 mw the junction temperature rise resulting from the power dissipation is calculated as: ja t j p t ? = ? p t is the total device dissipation, and ja is the package thermal resistance, which is 50c/w for the irf7413. the junction tem- perature rise is then: ? t j = 0.556w . 50c/w = 27.8 this is a modest temperature rise, so no special heat sinking is required when laying out the mosfet.
14 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com designing the loop there are two aspects concerning the loop design. one is the power train design and the other is the external compensation design. a good loop design is a combination of the two. in the sc1403, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, out- put capacitance, and the esr of the output caps. the low fre- quency gain is dominated by the output load impedance and the effective current sense resistor. inherent to virtual current sense tm , there is one additional low frequency pole sitting between 100hz and 1khz and a zero between 15khz and 25khz. to compensate for the sc1403 is easy since the output of error amplifier comp pin is available for external compensation. a traditional pole-zero- pole compensation is not necessary in the design using sc1403. to ensure high phase margin at crossover frequency while mini- mizing the component count, a simple high frequency pole is usu- ally sufficient. in the reference design below, single-pole compen- sation method is demonstrated. and the loop measurement re- sults are compared to those obtained from the simulation model. transient response is also done to validate the model. also, to help speed up the design process, a list of recommended output caps vs compensation caps value is given in table i. single-pole compensation method given parameters: vin = 19v, vout = 3.3v @ 2.2a, output impedance, ro = 3.3v/2.2a = 1.5 ? , panasonic sp cap, co = 180uf, resr = 15 ? m , output inductor, lo = 4.7uh switching frequency, fs = 300khz simulated control-to-output gain & phase response (up to 100khz) is plotted below. -50 -40 -30 -20 -10 0 10 20 30 40 50 100 1000 10000 100000 f (hz) gai n ( db) -200 -150 -100 -50 0 50 100 150 200 100 1000 10000 100000 f (hz) phase (deg) measured control-to-output gain & phase response (up to 100khz) is plotted below. -50 -40 -30 -20 -10 0 10 20 30 40 50 100 1000 10000 100000 f (hz) gai n (db) -200 -150 -100 -50 0 50 100 150 200 100 1000 10000 100000 f (hz) phase (deg) single-pole compensation of the error amplifier is achieved by connecting a 100pf capacitor from the comp pin of the sc1403 to ground. the simulated feedback gain & phase response (up to 100khz) is plotted below. applications information (cont.)
15 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com applications information (cont.) -15 -10 -5 0 5 10 15 20 25 100 1000 10000 100000 f (hz) gai n ( db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 1000 10000 100000 f (hz) phase ( deg) measured feedback gain & phase responses (up to 100khz) is plotted below. -15 -10 -5 0 5 10 15 20 25 100 1000 10000 100000 f (hz) gai n (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 100 1000 10000 100000 frequency (hz) phase (deg) simulated overall gain & phase responses (up to 100khz) is plot- ted below. -80 -60 -40 -20 0 20 40 60 80 100 1000 10000 100000 f (hz) gai n ( db) -20 0 20 40 60 80 100 120 140 160 180 100 1000 10000 100000 f (hz) phase ( deg)
16 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com applications information (cont.) measured overall gain & phase response of the single-pole com- pensation using sc1403 is plotted below. -20 -10 0 10 20 30 40 50 60 100 1000 10000 100000 f (hz) gai n ( db) -20 0 20 40 60 80 100 120 140 160 180 100 1000 10000 100000 f (hz) phase (deg) table i. recommended compensation cap for different output capacitance. p a c t u p t u on o i t a s n e p m o c d e d n e m m o c e r e u l a v p a c f 0 8 1 = f p 0 0 2 f 0 0 0 1 >f p 0 3 3
17 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com 3.3v psa ve disabled vin = 10v, iload= 0a to 3a 3.3v psa ve enabled vin = 19v, iload= 0a to 3a typical characteristics transient response using single-pole (capacitive) compensation is shown on the following pages. the load steps are from 0a to 3a and 3a to 6a. the applied di/dt is 2.5a/usec. 3.3v psa ve enabled vin = 10v, iload= 0a to 3a 3.3v forced-continuous vin = 10v, iload= 3a to 6a
18 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com 3.3v psa ve disabled vin = 19v, iload= 0a to 3a 5.0v psa ve enabled vin = 10v, iload= 0a to 3a 3.3v forced continuousvin = 19v, iload= 3a to 6a 5.0v psa ve disabled vin = 10v, iload= 0a to 3a typical characteristics (cont.)
19 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com 5.0v forced continuous vin = 10v, iload= 3a to 6a 5.0v psa ve enabled vin = 19v, iload= 0a to 3a 5.0v psa ve disabled vin = 19v, iload= 0a to 3a 5.0v forced continuous vin = 19v, iload= 3a to 6a typical characteristics (cont.)
20 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com applications information input capacitor selection and out-of-phase switching the sc1403 uses out-of-phase switching between the two converters to reduce input ripple current, allowing smaller, cheaper input capacitors compared to in-phase switching. the figure below shows in-phase switching. i3in is the input current drawn by the 3.3v converter, i5in is the input current drawn by the 5v converter. the two converters start each switching cycle simultaneously, causing in a significant amount of overlap. this overlap increases the peak current. the total input current to the converter is the third trace, iin, which shows how the two currents add together. the fourth trace shows the current flowing in and out of the input capacitors. i3in i5in iin average icap 0 0 d3 d5 the next figure shows out-of-phase switching. the 3.3v and 5v converters are spaced apart, thus there is no overlap. this gives two benefits. the peak current is reduced, and the effective switch frequency is raised; both of which make filtering easier. the third trace shows the total input current, and the fourth trace shows the current flowing in and out of the input capacitors. the rms value of the capacitor current is significantly lower than the in-phase case, which allows for smaller capacitors. i3in i5in icap iin average 0 0 d3 d5 as the input voltage is reduced, the duty cycle of both converters increases. for all input voltages less than 8.3v it is impossible to prevent overlap when producing 3.3v and 5v outputs, regardless of the phase relationship between the two converters. overlap can be seen in the following figure. i5in iin 0 average icap 0 period phase lead d3 d5 from an input filter standpoint it is desirable to minimize the overlap; but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, to prevent the two converters from affecting each other due to switching noise. the sc1403 keeps the turn-on and turn-off transitions separated in time by changing the phase relationship between the converter depending on the input voltage. the following table shows the phase relationship between 3v and 5v turn-on, based on input voltage. t u p n it u p n i t u p n i t u p n it u p n i e g a t l o ve g a t l o v e g a t l o v e g a t l o ve g a t l o v e g d e g n i s i r v 5 o t v 3 m o r f d a e l e s a h pe g d e g n i s i r v 5 o t v 3 m o r f d a e l e s a h p e g d e g n i s i r v 5 o t v 3 m o r f d a e l e s a h p e g d e g n i s i r v 5 o t v 3 m o r f d a e l e s a h pe g d e g n i s i r v 5 o t v 3 m o r f d a e l e s a h p v 6 . 9 > n i v. d o i r e p g n i h c t i w s f o % 1 4 . v 5 d n a v 3 n e e w t e b p a l r e v o g n i h c t i w s o n n i v > v 6 . 9 v 7 . 6 > . d o i r e p g n i h c t i w s f o % 9 5 s u o e n a t l u m i s t n e v e r p o t p a l r e v o l l a m s . g n i h c t i w s v 5 / v 3 n i v > 7 . 6. d o i r e p g n i h c t i w s f o % 4 6 s u o e n a t l u m i s t n e v e r p o t p a l r e v o l l a m s . g n i h c t i w s v 5 / v 3
21 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com applications information (cont.) input ripple current calculations: the following equations provide quick approximations for input ripple current: cycle duty 3v v v d in = = / 3 . 3 3 cycle duty 5v v v d in = = / 5 5 current load dc 3v i = 3 current load dc 5v i = 5 d ovl = overlapping duty cycle of the 3v and 5v pulses (varies according to input voltage) in ovl v 9.6v for 0 d = 9.6v v 6.7v for 0.41) - (d5 d in ovl < = 7 . 6 v for 0.36) - (d5 d in ovl < = current input dc average i in = 5 5 3 3 d i d i i in ? + ? = in rms sw v from drawn current rms i = _ 5 3 2 5 5 3 3 2 2 _ 2 i i d i d i d i ovl rms sw ? ? ? + ? + ? = 2 2 in_ave sw_rms i i + = rms_cap i the worst-case ripple current varies by application. for the case of i3 = i5 = 6a, the worst-case ripple occurs at vin = 7.5v, at which point the rms capacitor ripple current is 4.2a. to handle this the reference design uses 4 paralleled ceramic capacitors, (murata grm32nf51e106z, 10 uf 25v, size 1210). each capacitor is rated at 2.2a. choosing synchronous mosfet and schottky diode since this is a buck topology, the voltage and current ratings of the synchronous mosfet are the same as the main switching mosfet. it makes sense cost- and volume-wise to use the same mosfet for the main switch as for the synchronous mosfet. therefore, irf7413 is used again in the design for synchronous mosfet. to improve overall efficiency, an external schottky diode is used in parallel to the synchronous mosfet. the freewheeling current is going into the schottky diode instead of the body diode of the synchronous mosfet, which usually has very high forward drop and slow transient behavior. it is really important when laying out the board to place both the synchronous mosfet and schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the mosfet and the schottky diode. the current rating of the schottky diode can be determined by the following equation: a 2 . 0 t n 100 i i s load avg _ f = ? = where 100nsec is the estimated time between the mosfet turn- ing off and the schottky diode taking over and ts = 3.33us. there- fore a schottky diode with a forward current of 0.5a is sufficient for this design. external feedback design in order to optimize the ripple voltage during power save mode, it is strongly recommended to use external voltage dividers (r10 and r9 for 5v power train; r8 and r11 for 3.3v power train) to achieve the required output voltages. in addition a 56pf (c22 for 5v and c21 for 3.3v) cap is recommended connecting from the output to both feedback pins (pin # 3 and #12). the signal-to- noise ratio is therefore increased due to the added zeros.
22 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com operation below 6v input the sc1403 will operate below 6v input voltage with careful design, but there are limitations. the first limitation is the maximum available duty cycle from the sc1403, which limits the obtainable output voltage. the design should minimize all circuit losses through the system in order to deliver maximum power to the output. a second limitation with operation below 6v is transient response. when load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. if duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. this problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. if an application requires 5v output from an input voltage below 6v, the following guidelines should be used: 1 - set the switching frequency to 200 khz (tie sync to gnd). this increases the maximum duty cycle compared to 300 khz operation. 2 - minimize the resistance in the power train. select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - minimize the pcb resistance for all traces carrying high current. this includes traces to the input capacitors, mosfets and diodes, inductor, current sense resistor, and output capacitor. 4 - minimize the resistance between the sc1403 circuit and the power source (battery, battery charger, ac adaptor). 5 - use low esr capacitors on the input to prevent the input voltage dropping during on-time. 6 - if large load transients are expected, high capacitance and low esr capacitors should be used on both the input and output. overvoltage test measuring the overvoltage trip point can be problematic. any buck converter with synchronous mosfets can act as a boost con- verter, sending energy from output to input. in some cases the energy sent to the input is enough to drive the input voltage be- yond normal levels, causing input overvoltage. to prevent this enable the sc1403 psave# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. semtech recommends the following circuit for measuring the ov- ervoltage trip point. d1 prevents the output voltage from damag- ing lab supply 1. r1 limits the amount of energy that can be cycled from the output to the input. r2 absorbs the energy that might flow from output to input, and d2 protects lab supply from pos- sible damage. the on5 signal is monitored to indicate when overvoltage occurs. initial conditions: both lab supplies set to zero volts no load connected to 3v or 5v psave# enabled (psave# tied to gnd) on5, on3 both enabled dvms monitoring on5 and the output under test oscilloscope probe connected to phase node of the output under test (not strictly required) set lab supply 2 to provide 10v at the sc1403 input. the phase node of the output being tested should show some switching ac- tivity. the on5 pin should be above 4v. slowly increase lab supply 1 until the output under test rises slightly above it?s normal dc level. as the input lab supply 1 in- creases, switching activity at the phase node will cease. the on5 pin should remain above 4v. increase lab supply 1 in very small increments, monitoring both on5 and the output under test. the overvoltage trip point is the highest voltage seen at the output before on5 pulls low (approxi- mately 0.3v). do not record the voltage seen at the output after on5 has pulled low; when on5 pulls low, the current flowing in d1 changes, corrupting the voltage seen at the output. 1k d1 e.g. 1n4004 r2 75 to dvm d1 e.g. 1n4004 vin supply r1 470 2 sc1403 evaluation board lab output test under 1 supply lab to dvm 1/2w on5 vl 1/2w applications information (cont.) sc1403 d2
23 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com typical characteristics 5v line regulation 4.99 5.00 5.01 5.02 5.03 10 12 14 16 18 20 22 24 vin (v) vout (v) 5v@0a 5v@3a 5v@6a 3.3v line regulation 3.31 3.32 3.33 3.34 10 12 14 16 18 20 22 24 vin (v) vout (v) 3.3v@0a 3.3v@3a 3.3v@6a
24 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com 5v load regulation @vin =19v 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0123456 iout (a) vout (v) 5v @ 25degc 5v @125degc 5v@-45degc 5v load regulation @ vin =10v 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 0123456 iout (a) vout (v) 5.0v@25degc 5.0v@125degc 5.0v@-45degc typical characteristics (cont.)
25 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com 3.3v load regulation @ vin = 19v 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0123456 iout (a) vout (v) 3.3v@25degc 3.3v@125degc 3.3v@-45degc 3.3v load regulation @ vin =10v 3.28 3.29 3.30 3.31 3.32 3.33 3.34 0123456 iout (a) vout (v) 3.3v@25degc 3.3v@125degc 3.3v@-45degc typical characteristics (cont.)
26 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com 5v efficiency 85% 87% 89% 91% 93% 95% 97% 0.01 0.1 1 10 iout (a) efficiency (%) 5v@19vin 5v@10vin 3.3v efficiency 70% 75% 80% 85% 90% 95% 0.01 0.1 1 10 iout (a) efficiency (%) 3.3v@19vin 3.3v@10vin typical characteristics (cont.)
27 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com evaluation board schematic s1 1 2 3 4 8 7 6 5 c28 1uf c1 10uf/25v c2 10uf/25v c5 10uf/25v c6 10uf/25v c29 1uf r18 1.3k r21 1.3k r1 10 c3 0.22uf r20 1.3k r19 1.3k c4 0.22uf d3 140t3 r16 1k r13 100k c10 0.1uf c20 no_pop c15 0.22uf c16 0.22uf d5 140t3 c12 0.1uf c34 no_pop c35 0.1uf c36 no_pop c37 0.01uf c39 1uf ref d q1 irf7413 4 1 2 3 5 6 7 8 psv # reset# psv# c22 56pf c21 56pf on3 shdn# d q3 irf7413 4 1 2 3 5 6 7 8 d q2 irf7413 4 1 2 3 5 6 7 8 3_3v vl vin vin ref reset# d q4 irf7413 4 1 2 3 5 6 7 8 vin fb5 c17 180uf/4v c27 0.01uf r22 no_pop r23 no_pop c7 100pf c13 zero_ohm c8 100pf c14 zero_ohm r3 no_pop r2 no_pop r12 2m r17 2m r15 2m r14 2m tit le size document number date: sheet sc1403 evaluation bo b 1 monday, march 29, 2004 comp3 v+ comp5 comp3 comp5 cmp3rc t-on 5 cmp5rc c25 1uf/16v d4 30bq015 c18 no_pop d2 30bq015 r7 0.005 c19 150uf/6.3v c9 4.7uf/35v d1 bat54a l1 6.8uh r6 0.005 c11 4.7uf/16v c26 0.1uf vl vl c33 0.1uf r4 0 r5 0 r9 4.9 r8 1.58k r10 4.99k r11 4.99k l2 6.8uh u1 sc1403 csh3 1 csl3 2 fb3 3 comp3 4 comp5 5 sync 6 time/on5 7 gnd 8 ref 9 psave 10 reset 11 fb5 12 csl5 13 csh5 14 seq 15 dh5 16 phase5 17 bst5 18 dl5 19 pgnd 20 vl 21 v+ 22 shdn 23 dl3 24 bst3 25 phase3 26 dh3 27 run/on3 28
28 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com m e t iy t i n a u qn o i t a n g i s e dr e b m u n t r a pn o i t p i r c s e dr e r u t c a f u n a me s a c 14 6 c , 5 c , 2 c , 1 c5 2 0 z 6 0 1 v 5 y 0 3 2 m r gv 5 2 , f u 0 1a t a r u m0 1 2 1 24 6 1 c , 5 1 c , 4 c , 3 cf u 2 2 . 06 0 8 0 32 8 c , 7 cf p 0 0 13 0 6 0 42 1 1 c , 9 cf u 7 . 4 51 9 2 c , 8 2 c , 5 2 cc i m a r e c f u 1 617 1 cr 1 8 1 g 0 e u - f e ev 4 , f u 0 8 1c i n o s a n a p 3 4 3 7 _ e s a c _ d 719 1 cr 1 5 1 j 0 e u - f e ev 3 . 6 , f u 0 5 1c i n o s a n a p 3 4 3 7 _ e s a c _ d 811 da 4 5 t a bl a u d , a m 0 0 2 , v 0 3 e d o n a x e t e z3 2 - t o s 92 5 d , 3 d3 t 0 4 1 s r b my k t t o h c s a 1 , v 0 4a l o r o t o mb m s 0 12 4 d , 2 d5 1 0 q b 0 3y k t t o h c s a 3 , v 5 1l a n o i t a n r e t n i r e i f i t c e r 1 12 2 l , 1 l8 r 6 - 7 2 1 r dh u 8 . 6 r o t c u d n i t m ss c i n o r t l i o c 2 14 4 q , 3 q , 2 q , 1 q3 1 4 7 f r il e n n a h c - n v 0 3 t e f s o m l a n o i t a n r e t n i r e i f i t c e r 8 o s 3 111 rm h o 0 13 0 6 4 12 5 r , 4 rm h o 03 0 6 5 12 e v i t s i s e r ( 7 r , 6 r ) y l n o g n i s n e s 3 4 b f 5 0 0 r 2 1 5 2 l s w m h o m 5e l a d y a h s i v2 1 5 2 6 126 1 rm h o k 13 0 6 8 111 us t i 3 6 4 c sm w p e l i b o m s c v h t i w r e l l o r t n o c h c e t m e s8 2 p o s s t evaluation board bill of materials
29 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com bottom assembly top assembly evaluation board layout
30 ? 2004 semtech corp. sc1403 preliminary power management united states patent no. 6,377,032 www.semtech.com layout guidelines as with any high frequency switching regulator design, a good pcb layout is very essential in order to achieve optimum noise, effi- ciency, and stability performance of the converter. before starting pcb layout, a careful layout strategy is strongly recommended. see the pcb layout in the sc1403 evaluation kit manual for example. in most applications, use fr4 with 4 or more layers and at least 2 ounce copper (for output current up to 6a). use at least one inner layer for ground connection. it is always a good practice to tie signal-ground and power-ground at one single point so that the signal-ground is not easily contaminated. high current paths should have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. properly decouple lines that pull large amounts of current in short periods of time. the following layout strategy should be used in order to fully utilize the potential of sc1403. a. power train arrangement. place power train components first. the following figure shows the recommended power train arrangement. q1 is the main switching fet, q2 is the synchronous rectifier fet, d1 is the schottky diode and l1 is the output inductor. the phase node, where the source of the upper switching fet and the drain of the synchronous rectifier meets, switches at very high rate of speed, and is generally the largest source of common-mode noise in the converter circuit. it should be kept to a minimum size consistent with its connectivity and current carrying requirements. also place the schottky diode as close to the phase node as possible to minimize the trace inductance, therefore reducing the efficiency loss due to the current ramp-up and down time. this becomes extremely important when the converter needs to handle high di/ dt requirement. vias between power components should be used only when necessary: if vias are required, use multiple vias to reduce the inter-component impedance, and keep the traces between vias and power components as short and wide as pos- sible. q2 d1 q1 l1 b. current sense. with dcr sensing: the connections from the rc network to the inductor should be kelvin connections directly at the inductor solder pads. place the capacitor close to the csh/csl pins on the sc1403, and connect to the capacitor using short direct traces. c l c out csh csl s c 1403 v out r1 r2 with resistive sensing: minimize the length of current sense signal traces. keep them less than 15mm. use kelvin connections as shown below; keep the traces parallel to each other and as close together as possible. csh csl rsns l s c 1403 c. gate drive. the sc1403 has built-in gate drivers capable of sinking/sourcing 1a pk-pk. upper gate drive signals are noisier than the lower ones, so place them away from sensitive analog circuits. make sure the lower gate traces are as close as possible to the sc1403 pins, and make both upper and lower gate traces as wide as possible. d. pwm placement (pins) and signal ground island. connect all analog grounds to a separate solid copper island plane, which connects to the sc1403?s gnd pin. this includes ref, fb3, fb5, comp3, comp5, sync, on3, on5, psv# and reset#. e. ground plane arrangement. there are several ways to tie the different grounds together (ana- log ground, input power ground, and output power ground). with a buck topology, the output is quiet compared to the input side. the output is the best place to tie the analog ground to the power ground, often through a 0 ? resistor. the input power ground and the output power ground can be tied together using internal planes.
31 ? 2004 semtech corp. sc1403 power management united states patent no. 6,377,032 www.semtech.com outline drawing - tssop-28 land pattern - tssop-28 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information

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